In standard CMOS technology, an n-FET device uses an As (or other donor) doped n-type polysilicon layer as a gate electrode, which is deposited on top of a semiconductor oxide or semiconductor oxynitride gate dielectric layer. The gate voltage is applied through this n-doped polysilicon layer to create an inversion channel in the p-type silicon underneath the gate dielectric layer. Similarly, a p-FET device uses a boron (or other donor) doped p-type polysilicon layer as a gate electrode, which is also deposited on top of a semiconductor oxide or semiconductor oxynitride gate dielectric layer. The gate voltage is applied through the p-doped polysilicon layer to create an inversion channel in the n-type silicon underneath the gate dielectric layer.
However, limitations of polysilicon gate electrodes are inhibiting further gains in the CMOS device performance. Future generations of device logic will be required to use replacement materials for the gate electrodes.
Specifically, metallic materials have been shown as promising gate electrode materials for achieving further gains in device performance.
However, integration of the metallic gate electrodes into the CMOS circuits has proven challenging. Specifically, for alternatives to the conventional gate structures (i.e., comprising p-doped and n-doped polysilicon gate electrodes) to be fully realized, the n-FET and p-FET devices of the CMOS circuits must comprise different metals, and complimentary metals with work functions that are equivalent to the p-doped and n-doped polysilicon gate electrodes must be integrated simultaneously to form the respective n-FET and p-FET gate structures in the CMOS circuits. Patterning, thermal budget restraints, and material interactions associated with front-end-of-line (FEOL) logic integration have been problematic for a number of candidate metal materials.
As the industry struggles to find metal solutions for the p-FET and n-FET gate structures, there is a need for CMOS circuits that contain heterogeneous n-FET and p-FET gate structures for achieving continuous gains in the CMOS device performance.